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<div class="header">
  <div class="summary">
<a href="#pub-attribs">Data Fields</a>  </div>
  <div class="headertitle">
<div class="title">cy_stc_dpll_lp_config_t Struct Reference<div class="ingroups"><a class="el" href="group__group__sysclk.html">SysClk       (System Clock)</a> &raquo; <a class="el" href="group__group__sysclk__pll.html">Phase Locked Loop (PLL)</a> &raquo; <a class="el" href="group__group__sysclk__pll__structs.html">Data Structures</a></div></div>  </div>
</div><!--header-->
<div class="contents">
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<div class="textblock"><p>Structure containing information for configuration of a DPLL-LP. </p>
<dl class="section note"><dt>Note</dt><dd>This structure is available only for CAT1D devices. </dd></dl>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a2a1e2cea223e57ee2acae160e6727d25"><td class="memItemLeft" align="right" valign="top"><a id="a2a1e2cea223e57ee2acae160e6727d25"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a2a1e2cea223e57ee2acae160e6727d25">feedbackDiv</a></td></tr>
<tr class="memdesc:a2a1e2cea223e57ee2acae160e6727d25"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG register, FEEDBACK_DIV (P) bits. <br /></td></tr>
<tr class="separator:a2a1e2cea223e57ee2acae160e6727d25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acdc8bb51f2d654929ca3ae744d3526e8"><td class="memItemLeft" align="right" valign="top"><a id="acdc8bb51f2d654929ca3ae744d3526e8"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#acdc8bb51f2d654929ca3ae744d3526e8">referenceDiv</a></td></tr>
<tr class="memdesc:acdc8bb51f2d654929ca3ae744d3526e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG register, REFERENCE_DIV (Q) bits. <br /></td></tr>
<tr class="separator:acdc8bb51f2d654929ca3ae744d3526e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0f3f1db34de99017ff1026e9341115f6"><td class="memItemLeft" align="right" valign="top"><a id="a0f3f1db34de99017ff1026e9341115f6"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a0f3f1db34de99017ff1026e9341115f6">outputDiv</a></td></tr>
<tr class="memdesc:a0f3f1db34de99017ff1026e9341115f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG register, OUTPUT_DIV bits. <br /></td></tr>
<tr class="separator:a0f3f1db34de99017ff1026e9341115f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a318ee048f46ac80093e2c526902f703d"><td class="memItemLeft" align="right" valign="top"><a id="a318ee048f46ac80093e2c526902f703d"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a318ee048f46ac80093e2c526902f703d">pllDcoMode</a></td></tr>
<tr class="memdesc:a318ee048f46ac80093e2c526902f703d"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG register, PLL_DCO_MODE bit. <br /></td></tr>
<tr class="separator:a318ee048f46ac80093e2c526902f703d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a706d645d66e4677af6d596fd79aa41ba"><td class="memItemLeft" align="right" valign="top"><a id="a706d645d66e4677af6d596fd79aa41ba"></a>
<a class="el" href="group__group__sysclk__fll__enums.html#ga777e08424e26c9cd8c2602b2114e716b">cy_en_fll_pll_output_mode_t</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a706d645d66e4677af6d596fd79aa41ba">outputMode</a></td></tr>
<tr class="memdesc:a706d645d66e4677af6d596fd79aa41ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG register, BYPASS_SEL bits. <br /></td></tr>
<tr class="separator:a706d645d66e4677af6d596fd79aa41ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae66ca35222bceb3bc5105e63812ddb32"><td class="memItemLeft" align="right" valign="top"><a id="ae66ca35222bceb3bc5105e63812ddb32"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#ae66ca35222bceb3bc5105e63812ddb32">fracDiv</a></td></tr>
<tr class="memdesc:ae66ca35222bceb3bc5105e63812ddb32"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG2 register, FRAC_DIV bits, only for CAT1B(B2),CAT1D devices. <br /></td></tr>
<tr class="separator:ae66ca35222bceb3bc5105e63812ddb32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aedd876434efabcb5a01b67253ea25999"><td class="memItemLeft" align="right" valign="top"><a id="aedd876434efabcb5a01b67253ea25999"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#aedd876434efabcb5a01b67253ea25999">fracDitherEn</a></td></tr>
<tr class="memdesc:aedd876434efabcb5a01b67253ea25999"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG2 register, FRAC_DITHER_EN bit, only for CAT1B(B2),CAT1D devices. <br /></td></tr>
<tr class="separator:aedd876434efabcb5a01b67253ea25999"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0b9599c1ea0d0abefe32b272ef5e17e1"><td class="memItemLeft" align="right" valign="top"><a id="a0b9599c1ea0d0abefe32b272ef5e17e1"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a0b9599c1ea0d0abefe32b272ef5e17e1">fracEn</a></td></tr>
<tr class="memdesc:a0b9599c1ea0d0abefe32b272ef5e17e1"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG2 register, FRAC_EN bit, only for CAT1B(B2),CAT1D devices. <br /></td></tr>
<tr class="separator:a0b9599c1ea0d0abefe32b272ef5e17e1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a57bfe58c437b973c3873c841c4922979"><td class="memItemLeft" align="right" valign="top"><a id="a57bfe58c437b973c3873c841c4922979"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a57bfe58c437b973c3873c841c4922979">sscgDepth</a></td></tr>
<tr class="memdesc:a57bfe58c437b973c3873c841c4922979"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG3 register, SSCG_DEPTH bits, only for CAT1B(B2),CAT1D devices. <br /></td></tr>
<tr class="separator:a57bfe58c437b973c3873c841c4922979"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a77d6a41ed79cad31f833021eda8f3fb2"><td class="memItemLeft" align="right" valign="top"><a id="a77d6a41ed79cad31f833021eda8f3fb2"></a>
uint8_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a77d6a41ed79cad31f833021eda8f3fb2">sscgRate</a></td></tr>
<tr class="memdesc:a77d6a41ed79cad31f833021eda8f3fb2"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG3 register, SSCG_RATE bits, only for CAT1B(B2),CAT1D devices. <br /></td></tr>
<tr class="separator:a77d6a41ed79cad31f833021eda8f3fb2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a83aa3ea8bce302a0720e5ad2fa1184a3"><td class="memItemLeft" align="right" valign="top"><a id="a83aa3ea8bce302a0720e5ad2fa1184a3"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a83aa3ea8bce302a0720e5ad2fa1184a3">sscgDitherEn</a></td></tr>
<tr class="memdesc:a83aa3ea8bce302a0720e5ad2fa1184a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG3 register, SSCG_DITHER_EN bit, only for CAT1B(B2),CAT1D devices. <br /></td></tr>
<tr class="separator:a83aa3ea8bce302a0720e5ad2fa1184a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ac516b0702132b921eba2b84d2acad9f7"><td class="memItemLeft" align="right" valign="top"><a id="ac516b0702132b921eba2b84d2acad9f7"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#ac516b0702132b921eba2b84d2acad9f7">sscgMode</a></td></tr>
<tr class="memdesc:ac516b0702132b921eba2b84d2acad9f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG3 register, SSCG_MODE bit, only for CAT1B(B2),CAT1D devices. <br /></td></tr>
<tr class="separator:ac516b0702132b921eba2b84d2acad9f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3341804ec3f278b214174d46ff19a010"><td class="memItemLeft" align="right" valign="top"><a id="a3341804ec3f278b214174d46ff19a010"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a3341804ec3f278b214174d46ff19a010">sscgEn</a></td></tr>
<tr class="memdesc:a3341804ec3f278b214174d46ff19a010"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG3 register, SSCG_EN bit, only for CAT1B(B2),CAT1D devices. <br /></td></tr>
<tr class="separator:a3341804ec3f278b214174d46ff19a010"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab5f451595fcc042c76cf2f6cbd3cd540"><td class="memItemLeft" align="right" valign="top"><a id="ab5f451595fcc042c76cf2f6cbd3cd540"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#ab5f451595fcc042c76cf2f6cbd3cd540">dcoCode</a></td></tr>
<tr class="memdesc:ab5f451595fcc042c76cf2f6cbd3cd540"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, DCO_CODE bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:ab5f451595fcc042c76cf2f6cbd3cd540"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0ebd45067b369e50454b87b7438b5c39"><td class="memItemLeft" align="right" valign="top"><a id="a0ebd45067b369e50454b87b7438b5c39"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a0ebd45067b369e50454b87b7438b5c39">accMode</a></td></tr>
<tr class="memdesc:a0ebd45067b369e50454b87b7438b5c39"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, ACC_MODE bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:a0ebd45067b369e50454b87b7438b5c39"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab9683590b6b98a9e231bb7b55ca03bc6"><td class="memItemLeft" align="right" valign="top"><a id="ab9683590b6b98a9e231bb7b55ca03bc6"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#ab9683590b6b98a9e231bb7b55ca03bc6">tdcMode</a></td></tr>
<tr class="memdesc:ab9683590b6b98a9e231bb7b55ca03bc6"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, TDC_MODE bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:ab9683590b6b98a9e231bb7b55ca03bc6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a8b562c03a1e0f7a80f2903bb9df1e3e5"><td class="memItemLeft" align="right" valign="top"><a id="a8b562c03a1e0f7a80f2903bb9df1e3e5"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a8b562c03a1e0f7a80f2903bb9df1e3e5">pllTg</a></td></tr>
<tr class="memdesc:a8b562c03a1e0f7a80f2903bb9df1e3e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, PLL_TG bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:a8b562c03a1e0f7a80f2903bb9df1e3e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a755e60dbe94ac02e7cd31a69283ecc32"><td class="memItemLeft" align="right" valign="top"><a id="a755e60dbe94ac02e7cd31a69283ecc32"></a>
bool&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a755e60dbe94ac02e7cd31a69283ecc32">accCntLock</a></td></tr>
<tr class="memdesc:a755e60dbe94ac02e7cd31a69283ecc32"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG4 register, ACC_CNT_LOCK bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:a755e60dbe94ac02e7cd31a69283ecc32"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a13200eea948a561bde8486349e333e43"><td class="memItemLeft" align="right" valign="top"><a id="a13200eea948a561bde8486349e333e43"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a13200eea948a561bde8486349e333e43">kiInt</a></td></tr>
<tr class="memdesc:a13200eea948a561bde8486349e333e43"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG5 register, KI_INT bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:a13200eea948a561bde8486349e333e43"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7bc81ed3c66afa6382a5d80814440c25"><td class="memItemLeft" align="right" valign="top"><a id="a7bc81ed3c66afa6382a5d80814440c25"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a7bc81ed3c66afa6382a5d80814440c25">kpInt</a></td></tr>
<tr class="memdesc:a7bc81ed3c66afa6382a5d80814440c25"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG5 register, KP_INT bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:a7bc81ed3c66afa6382a5d80814440c25"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:acccc04a61b05d4db7e718a07bfc1a0fb"><td class="memItemLeft" align="right" valign="top"><a id="acccc04a61b05d4db7e718a07bfc1a0fb"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#acccc04a61b05d4db7e718a07bfc1a0fb">kiAccInt</a></td></tr>
<tr class="memdesc:acccc04a61b05d4db7e718a07bfc1a0fb"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG5 register, KI_ACC_INT bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:acccc04a61b05d4db7e718a07bfc1a0fb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0a43a33131e6571c78ba0a4f03fc463c"><td class="memItemLeft" align="right" valign="top"><a id="a0a43a33131e6571c78ba0a4f03fc463c"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a0a43a33131e6571c78ba0a4f03fc463c">kpAccInt</a></td></tr>
<tr class="memdesc:a0a43a33131e6571c78ba0a4f03fc463c"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG5 register, KP_ACC_INT bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:a0a43a33131e6571c78ba0a4f03fc463c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0588ff2bb117affa6ef6736cfe6fed82"><td class="memItemLeft" align="right" valign="top"><a id="a0588ff2bb117affa6ef6736cfe6fed82"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a0588ff2bb117affa6ef6736cfe6fed82">kiFrac</a></td></tr>
<tr class="memdesc:a0588ff2bb117affa6ef6736cfe6fed82"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG6 register, KI_FRACT bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:a0588ff2bb117affa6ef6736cfe6fed82"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a15cb653c8a5ba510762dec1bf59e5226"><td class="memItemLeft" align="right" valign="top"><a id="a15cb653c8a5ba510762dec1bf59e5226"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a15cb653c8a5ba510762dec1bf59e5226">kpFrac</a></td></tr>
<tr class="memdesc:a15cb653c8a5ba510762dec1bf59e5226"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG6 register, KP_FRACT bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:a15cb653c8a5ba510762dec1bf59e5226"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a34057f67990d788b8581b344db820998"><td class="memItemLeft" align="right" valign="top"><a id="a34057f67990d788b8581b344db820998"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a34057f67990d788b8581b344db820998">kiAccFrac</a></td></tr>
<tr class="memdesc:a34057f67990d788b8581b344db820998"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG6 register, KI_ACC_FRACT bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:a34057f67990d788b8581b344db820998"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a76822495180aa1787c1e8c6ee7a529e9"><td class="memItemLeft" align="right" valign="top"><a id="a76822495180aa1787c1e8c6ee7a529e9"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a76822495180aa1787c1e8c6ee7a529e9">kpAccFrac</a></td></tr>
<tr class="memdesc:a76822495180aa1787c1e8c6ee7a529e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG7 register, KP_ACC_FRACT bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:a76822495180aa1787c1e8c6ee7a529e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae28a6d624d4d1e0a48dfcf453e5ee5cc"><td class="memItemLeft" align="right" valign="top"><a id="ae28a6d624d4d1e0a48dfcf453e5ee5cc"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#ae28a6d624d4d1e0a48dfcf453e5ee5cc">kiSscg</a></td></tr>
<tr class="memdesc:ae28a6d624d4d1e0a48dfcf453e5ee5cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG7 register, KI_SSCG bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:ae28a6d624d4d1e0a48dfcf453e5ee5cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abed2ee86490a35988a7573070ab9e4da"><td class="memItemLeft" align="right" valign="top"><a id="abed2ee86490a35988a7573070ab9e4da"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#abed2ee86490a35988a7573070ab9e4da">kpSscg</a></td></tr>
<tr class="memdesc:abed2ee86490a35988a7573070ab9e4da"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG7 register, KP_SSCG bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:abed2ee86490a35988a7573070ab9e4da"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a00e804ce2364321da2318408f4fabdef"><td class="memItemLeft" align="right" valign="top"><a id="a00e804ce2364321da2318408f4fabdef"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#a00e804ce2364321da2318408f4fabdef">kiAccSscg</a></td></tr>
<tr class="memdesc:a00e804ce2364321da2318408f4fabdef"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG7 register, KI_ACC_SSCG bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:a00e804ce2364321da2318408f4fabdef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aedcb041b8765e4ce2477d8b878f9b1fc"><td class="memItemLeft" align="right" valign="top"><a id="aedcb041b8765e4ce2477d8b878f9b1fc"></a>
uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structcy__stc__dpll__lp__config__t.html#aedcb041b8765e4ce2477d8b878f9b1fc">kpAccSscg</a></td></tr>
<tr class="memdesc:aedcb041b8765e4ce2477d8b878f9b1fc"><td class="mdescLeft">&#160;</td><td class="mdescRight">CONFIG7 register, KP_ACC_SSCG bits, only for CAT1B(B2), devices. <br /></td></tr>
<tr class="separator:aedcb041b8765e4ce2477d8b878f9b1fc"><td class="memSeparator" colspan="2">&#160;</td></tr>
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